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IMAPS Chesapeake Chapter Summer Techncial Symposium

Aug 01, 2012 03:00pm -
Aug 01, 2012 06:30pm

Event Description



3:00 Registration, Participant Introductions, and Brief Opening Remarks.


3:30   “"Packaging for Solar Grid-tie Inverters."

                Dr. Dimosthenis Katsis, Chief Technology Officer of Athena Energy, LLC


4:15  High Temperature Silicon Carbide Switches and Rectifiers.”

               Dr. Ranbir Singh, President of GeneSIC Semiconductor.


4:45 Brief break.


5:00  Optimized Acoustic Microscopy Screening for Multilayer Ceramic Capacitors.”

               Dr. Andrew Kostic, Senior Project Leader at the Aerospace Corporation


5:30 Event wrap-up. Ideas for next event. Other business.


5:45 Dinner


6:30 Event Concludes





Wednesday, August 1, 3:00


Applied Physics Laboratory of Johns Hopkins University

Howard County Room #3

11100 Johns Hopkins Road, Laurel, MD 20723

Click here for map and directions (www.jhuapl.edu)


Enter in the area marked Lobby 1 and check-in with APL staff.

Call Bruce Romenesko of APL at 240-228-8065 for on-site info. only.



Registration fees and member discounts to cover the costs:

IMAPS Members-$25, non-members-$35, and students with ID-$5.00.


Only on-line registration by credit card guarantees a dinner seating.

On-line registration ends on Friday, July 27 at COB.


Checks/cash only on-site. Additional fee at the door of $5.00.



Presenter BIOs and ABstracts

Dr. Dimosthenis (Dimos) Katsis, Chief Technology Officer of Athena Energy, LLC


Bio: Dimosthenis Katsis is an electrical engineer and researcher in the field of electronics and solar energy. He graduated from Virginia Tech, getting his Bachelors and Masters Degrees in 1995 and 1997.  Dimos continued to study power electronics and electric vehicle design at the Virginia Power Electronics Center and again after joining General Electric as an Edison Engineering fellow.  He contributed to the development of a new generation of high power AC drives for steel mills and power semiconductor characterization.  Dimos then returned to Virginia Tech to pursue a doctorate in Electrical Engineering, finishing in Jan. 2003. He then joined the U.S. Army Research Laboratory the same year to develop power systems for the battlefield.  Dimos left the army labs to begin a new company dedicated to solar power products and reliability engineering in power electronics.  He presently teaches at the Johns Hopkins University’s Whiting School of Electrical and Computer Engineering.




 Microinverter design and packaging for reliability microinverters are becoming ubiquitous in the renewable
energy world as an inexpensive and cost-effective way to provide photovoltaic power to the grid. Their small
 form-factor and high power density creates various challenges for efficient design in the power semiconductor, capacitor, and magnetics components. We will investigate some of the design tradeoffs
 and decisions made in the development of microinverter systems for high reliability. A sample system will be
presented to demonstrate these relationships.


Dr. Ranbir Singh, President of GeneSIC Semiconductor

Dr. Ranbir Singh founded GeneSiC Semiconductor Inc. in 2004.  He has developed critical understanding and published on a wide range of SiC power devices including PiN, JBS and Schottky diodes, MOSFETs, IGBTs, thyristors and field controlled thyristors.  He has co-authored over 120 publications in various refereed journals and conference proceedings and is an inventor on 26 issued US patents.  He conducted research on SiC power devices first at Cree Inc., and then at the National Institute of Standards and Technology (NIST), Gaithersburg MD.  He has served on the Technical committee of the International Symposium on Power Semiconductor Devices and ICs (ISPSD) from 2002-04. He earned his MS & PhD degrees from North Carolina State University.


1200 V Class Super-High Current Gain Transistors or SJTs developed by GeneSiC are distinguished by low leakage currents of < 100 µA at 325° C operating temperature, turn-on and turn-off switching transients of < 15 ns at 250 °C, maximum Common Source current gains of 88 and low on-resistance of 5.8 mΩ-cm2.  Results from detailed on-state, blocking, switching and reliability characterization of 1200 V-class 4 mm2 and 16 mm2 SiC SJTs are presented.  SiC Schottky rectifiers with >250o C junction temperatures with low leakage currents are presented with a detailed analysis of their ideality factors.  GeneSiC’s Schottky rectifiers resulted in a distinct positive temperature co-efficient of avalanche breakdown and offers a much smaller increase in leakage current with temperature from 25o C to 250o C.



Dr. Andrew Kostic, Senior Project Leader at the Aerospace Corporation


Dr. Kostic is a Senior Project Leader at The Aerospace Corporation working with electronic, electrical, and electromechanical parts, materials, and processes.  He is a recognized authority on environmental stress screening (ESS).  Andy has taught classes in screening of electronics for over 20 years for many organizations including Motorola, University of Wisconsin-Milwaukee, Hong Kong Productivity Council, and the Organizational Effectiveness Institute.  Dr. Kostic is the author of numerous technical papers and is a Senior Member of the IEEE.



A program was having a significant number of early life failures due to infant mortality of Multilayer Ceramic Chip Capacitors (MLCC). Board rework was difficult and expensive due to the locations of the MLCC and the complexity of the board. The proposed solution was to develop an improved acoustic microscopy screen for MLCC with latent defects 30 MHz acoustic microscopy screening is unable to detect a significant number of life limiting defects MLCC. 50 MHz screening is able to detect the defects that were missed at 30 MHz. There was not a 100% link between the detection of an anomaly and a device failure in this study. Four factors were identified that correlate strongly with MLCC failure rates: (1) Dielectric composition (2) Delaminations (3) Size (4) Capacitance value greater than 100,000 pF MLCC program requirements have been changed to require 50 MHz two sided C-Mode Scanning Acoustic Microscope (C-SAM) 100% lot inspection. The enhanced screen had positive cost impact. A different transducer was required in a screen that was already in place. There was increased screen fallout of MLCCs but the reduced board rework/repair costs more than offset the part cost. Parts passing the enhanced screen have not shown the early life failure issue. Additional work is necessary to determine the effects on MLCC reliability of defects other than delaminations.

Event Type:Chapter
Category:Chapter Meeting
Early registration ends on Jun 20, 2012.
Regular registration starts on Jun 21, 2012 and ends on Jul 31, 2012.
Late registration starts on Aug 01, 2012.
(GMT-05:00) Eastern Time (US & Canada)


Registration Fees
Fee TypeEarlyRegularLate
Member Fee: $25.00$25.00$30.00
Non-Member Fee: $35.00$35.00$40.00
Member Fee: $5.00$5.00$5.00
Non-Member Fee: $5.00$5.00$5.00
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