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Northern California Chapter Lunch Presentation on Advanced Backend Technology

Aug 01, 2012 11:30am -
Aug 01, 2012 02:30pm

Event Description

Northern California Chapter


Lunch Presentation on Wednesday, August 1   
Advanced Backend Technology


Jesse Wang, Deputy Director

Backend Technology Support & Marketing

TSMC North America



As semiconductors continue to scale, challenges of chip-package integration (CPI) at advanced technology nodes continue to mount due to requirements for smaller bump pitches, larger die sizes, and lead-free packaging.  The challenges will be harder to enable high-end applications that require higher memory bandwidth, lower power, and demanding 3-D die stacking that features micro bumps and through silicon via.  TSMC focuses on CPI addressing integration of advanced silicon interconnects and testing technologies.  This adds value for shorter time to market, faster yield learning and better cycle time control.  These include silicon Chip on Wafer on Substrate (CoWoS) for high performance applications and copper Bump-on-Trace (BOT) for mobile applications. 

Event Type:Chapter
Category:Chapter Meeting
Early registration ends on Jul 08, 2012.
Regular registration starts on Jul 09, 2012 and ends on Jul 30, 2012.
Late registration starts on Jul 31, 2012.
(GMT-08:00) Pacific Time (US & Canada), Tijuana


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