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Description Return to Event
Session Details

PDC B1: Emerging Challenges in Semiconductor Packaging (8-10am)
(Event: IMAPS 2017 - 50th International Symposium on Microelectronics)

Oct 09, 2017 8:00am - Oct 09, 2017 10:00am
Session Type: PDC

Description

Track B:
Next Generation Packaging Challenges

B1: Emerging Challenges in Semiconductor Packaging
Instructor: Raja Swaminathan, Intel Corp.

 

Course description:

The course will introduce role of packaging in the interconnect hierarchy and introduce packaging trends per industry. We will then deep dive into the key elements driving the definition of a package architecture (scaling challenges, high speed signaling, power delivery, thermo-mechanical integration as well as thermal challenges). The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed.

 

The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

 

Who Should Attend?

The attendees are expected to have an in depth understanding of the fundamentals of packaging.

 

Biography:

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 18 patents and 23 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University. 

 

  

Session Fees
Fee TypeMember FeeNon-Member Fee
This session is free
Early: $300.00 $300.00
Regular: $400.00 $400.00
Late: $400.00 $400.00

 
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