C1: 2.5D IC Integration and TSV-less Interposers
Instructor: John Lau, ASM Pacific Technology
An interposer (2.5D IC integration) is just a piece of dummy silicon (a part of the package substrate) without devices but with TSVs (through-silicon vias) and RDLs (redistribution layers). Because TSVs involve many semiconductor processes, e.g., DRIE, PECVD, PVD, ECD, CMP, and Cu revealing, TSV technology is very expensive for a package substrate. In order to lower the cost, enhance the electrical performance, and reduce the package profile, the TSV should be eliminated from the interposer, i.e., a TSV-less interposer.
In this PDC, some TSV-less interposers proposed in the past three years such as those developed by Xilinx/SPIL, Amkor, ASE, Mediatek, Intel, ITRI, Shinko, Cisco, Sony, and Samsung will be presented and discussed. The materials and process of TSV and 2.5D IC integration will be briefly mentioned first. The future trends of 2.5D IC integration will also be presented.
Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of the microelectronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. All the materials are based on the papers and books published in the past 3 years.
With more than 38 years of R&D and manufacturing experience in semiconductor packaging, John Lau has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill Book Company, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill Book Company, 2011), TSV for 3D Integration, (McGraw-Hill Book Company, 2013), and 3D IC Integration and Packaging (McGraw-Hill Book Company, 2016).