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Description Return to Event
Session Details

PDC D2: A Methodology for Understanding the Reliability of Electronic Packaging (10:30am-12:30pm)
(Event: IMAPS 2017 - 50th International Symposium on Microelectronics)

Oct 09, 2017 10:30am - Oct 09, 2017 12:30pm
Session Type: PDC

Description

Track D:
Reliability

D2: A Methodology for Understanding the Reliability of Electronic Packaging
Instructor: Greg Caswell, DfR Solutions

 

Course description:

Reliability is the measure of a product’s ability to perform its specified function at the customer’s facility, in their use environment, over the desired lifetime.  Designing for reliability is the method for ensuring the reliability of a product or system during the design stage, before a physical prototype is produced is paramount.

 

This course will describe the failure modes associated with die attach, wire bonding, and solder joints using a Physics of Failure approach.  Strain energy equations will be discussed for the potential failure modes to help the student facilitate prediction of failure.

 

The course will then discuss the relatively new failure mechanism, that of silicon wearout.  As gate geometries have continued to shrink, the susceptibility of the device to fail has increased, to a point where some of the newer 14 nm feature devices will not hold up well in high reliability applications.  We will look at the intrinsic mechanisms of ICs to understand their susceptibility based on environments.

 

The next module of the course will demonstrate a methodology for using Physics of Failure to assess the failure modes associated with the populated circuit board, looking at issues such as thermos-mechanical fatigue, thermal effects, and the more probabilistic mechanisms like CAF and IMC fracture from mechanical shock.  The approach will show how to predict failure at this level.

 

Finally, the course will introduce a method for assessing the microvias in a package to identify the highest stressor points and provide an approach for obviation.  Lastly, a short presentation on Electrostatic Discharge (ESD) and how to mitigate it will be presented.

 

Who Should Attend?

Engineers and managers who have a vested interest in producing high reliability devices and systems that meet their customer’s expectations.

 

Biography:

Greg Caswell, a Senior Member of the Technical Staff for DfR Solutions, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 45 years. Prior to joining DfR Greg was the Vice President of Engineering at Reactive Nanotechnology (RNT), where he led application development for the RNT Nanofoil® and ensured a successful transition of product technology to Indium Corporation. His previous appointments include Vice President of Business Development for Newport Enterprises, Director of Engineering for VirTex Assembly Services, and Technical Director at Silicon Hills Design. He has presented over 250 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events.  He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space. B.A., Management (St. Edwards University). B.S., Electrical Engineering (Rutgers University)

 

  

Session Fees
Fee TypeMember FeeNon-Member Fee
This session is free
Early: $300.00 $300.00
Regular: $400.00 $400.00
Late: $400.00 $400.00

 
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