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Description Return to Event
Session Details

PDC A4: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar (3:30-5:30pm)
(Event: IMAPS 2017 - 50th International Symposium on Microelectronics)

Oct 09, 2017 3:30pm - Oct 09, 2017 5:30pm
Session Type: PDC

Description

Track A:
Intro to Microelectronics Packaging

A4: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Instructor: Mark Gerber, ASE US, Inc.

 

Course description:

This PDC course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective.   Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. The understanding The trade-offs between The traditional Solder based Flip Chip and Copper Pillar is key in determining The silicon device layout and The type of design rules that can be leveraged for new products. as part of This course, The Solder Bump and Copper Pillar Bump structure formation will be reviewed as well as multiple Cu Pillar Flip Chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions. Current market trends have led to additional questions regarding the longevity of Flip Chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

 

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.  

 

  

Session Fees
Fee TypeMember FeeNon-Member Fee
This session is free
Early: $300.00 $300.00
Regular: $400.00 $400.00
Late: $400.00 $400.00

 
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